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16-bit 100 ksps pulsar tm unipolar adc with reference ad7651 features throughput: 100 ksps 16-bit resolution analog input voltage range: 0 v to 2.5 v no pipeline delay parallel and serial 5 v/3 v interface spi ? /qspi tm /microwire tm /dsp compatible single 5 v supply operation power dissipation 16 mw typ, 160 w @ 1 ksps without ref 38 mw typ with ref 48-lead lqfp and 48-lead lfcsp packages pin-to-pin compatible with pulsar adcs applications data acquisition instrumentation digital signal processing spectrum analysis medical instruments battery-powered systems process control general description the ad7651 is a 16-bit, 100 ksps, charge redistribution sar analog-to-digital converter that operates from a single 5 v power supply. the part contains a high speed 16-bit sampling adc, an internal conversion clock, internal reference, error correction circuits, and both serial and parallel system inter- face ports. the ad7651 is fabricated using analog devices high perform- ance, 0.6 micron cmos process, with correspondingly low cost, and is available in a 48-lead lqfp and a tiny 48-lead lfcsp with operation specified from C40c to +85c. functional block diagram 02964-0-001 switched cap dac 16 control logic and calibration circuitry clock ad7651 data[15:0] busy rd cs ser/p a r ob/2 c ognd ovdd dgnd dvdd avdd agnd ref refgnd in ingnd pd reset serial port parallel interface cnvst ref refbufin pdbuf pdref byteswap figure 1. functional block diagram table 1. pulsar selection type/ksps 100C250 500C570 800C 1000 pseudo- differential ad7651 ad7660/ ad7661 ad7650/ ad7652 ad7664/ ad7666 ad7653 ad7667 true bipolar ad7663 ad7665 ad7671 true differential ad7675 ad7676 ad7677 18-bit ad7678 ad7679 ad7674 multichannel/ simultaneous ad7654 ad7655 product highlights 1. fast throughput. the ad7651 is a 100 ksps, charge redistribution, 16-bit sar adc with internal error correction circuitry. 2. internal reference. the ad7651 has an internal reference with a typical temperature drift of 7 ppm/c. 3. single-supply operation. th e ad7651 operates from a single 5 v supply. its power dissipation decreases with throughput. 4. serial or parallel interface. versatile parallel or 2-wire serial interface arrangement is compatible with both 3 v and 5 v logic. rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2003 analog devices, inc. all rights reserved.
ad7651 table of contents specifications ..................................................................................... 3 timing specifications ....................................................................... 5 absolute maximum ratings ............................................................ 7 pin configuration and function descriptions ............................. 8 definitions of specifications ......................................................... 11 typical performance characteristics ........................................... 12 circuit information ........................................................................ 15 converter operation .................................................................. 15 typical connection diagram .................................................... 17 power dissipation versus throughput .................................... 19 conversion control .................................................................... 19 digital interface .......................................................................... 20 parallel interface ......................................................................... 20 serial interface ............................................................................ 20 master serial interface ............................................................... 21 slave serial interface .................................................................. 22 microprocessor interfacing ....................................................... 24 application hints ............................................................................ 25 bipolar and wider input ranges .............................................. 25 layout .......................................................................................... 25 evaluating the ad7651s performance .................................... 25 outline dimensions ....................................................................... 26 ordering guide ........................................................................... 26 revision history revision 0, initial version. rev. 0 | page 2 of 28
ad7651 specifications table 2. C40c to +85c, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted parameter conditions min typ max unit resolution 16 bits analog input voltage range v in C v ingnd 0 v ref v operating input voltage v in C0.1 +3 v v ingnd C0.1 +0.5 v analog input cmrr f in = 10 khz 65 db input current 100 ksps throughput 1.1 a input impedance 1 throughput speed complete cycle 10 s throughput rate 0 100 ksps dc accuracy integral linearity error C6 +6 lsb 2 no missing codes 15 bits differential linearity error C2 +3 lsb transition noise 0.7 lsb unipolar zero error, t min to t max 3 5 lsb unipolar zero error temperature drift 3 0.25 ppm/c full-scale error, t min to t max 3 ref = 2.5 v 0.12 % of fsr full-scale error temperature drift 0.6 ppm/c power supply sensitivity avdd = 5 v 5% 2 lsb ac accuracy signal-to-noise f in = 45 khz 86 db 4 spurious free dynamic range f in = 45 khz 98 db total harmonic distortion f in = 10 khz C98 db f in = 45 khz C98 db signal-to-(noise + distortion) f in = 45 khz 86 db C60 db input, f in = 45 khz 30 db C3 db input bandwidth 800 khz sampling dynamics aperture delay 2 ns aperture jitter 5 ps rms transient response full-scale step 8.75 s reference internal reference voltage v ref @ 25c 2.48 2.5 2.52 v internal reference temperature drift C40c to +85c 7 ppm/c line regulation avdd = 5 v 5% 24 ppm/v turn-on settling time c ref = 10 f 5 ms temperature pin voltage output @ 25c 300 mv temperature sensitivity 1 mv/c output resistance 4.3 k? external reference voltage range 2.3 2.5 avdd C 1.85 v external reference current drain 100 ksps throughput 35 a rev. 0 | page 3 of 28
ad7651 parameter conditions min typ max unit digital inputs logic levels v il C0.3 +0.8 v v ih 2.0 dvdd + 0.3 v i il C1 +1 a i ih C1 +1 a digital outputs data format 5 pipeline delay 6 v ol i sink = 1.6 ma 0.4 v v oh i source = C500 a ovdd C 0.6 v power supplies specified performance avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.7 5.25 7 v operating current 100 ksps throughput avdd 8 with reference and buffer 6.2 ma avdd 9 reference and buffer alone 3 ma dvdd 10 1.5 ma ovdd 10 18 a power dissipation without ref 10 100 ksps throughput 16 25 mw 1 ksps throughput 160 w power dissipation with ref 10 100 ksps throughput 38 45 mw temperature range 11 specified performance t min to t max C40 +85 c 1 see section. analog input 2 lsb means least significant bit. with the 0 v to 2.5 v input range, 1 lsb is 38.15 v. 3 see section. these specifications do not include the error contribution from the external referen ce. definitions of specifications 4 all specifications in db are referred to a full-scale input fs. te sted with an input signal at 0.5 db below full-scale, unless otherwise specified. 5 parallel or serial 16-bit. 6 conversion results are available imme diately after completed conversion. 7 the max should be the minimum of 5.25 v and dvdd + 0.3 v. 8 with ref, pdref and pdbuf are low; wi thout ref, pdref and pdbuf are high. 9 with pdref, pdbuf low and pd high. 10 tested in parallel reading mode 11 consult factory for extend ed temperature range. rev. 0 | page 4 of 28
ad7651 timing specifications table 3. C40c to +85c, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted parameter symbol min typ max unit refer to figure 26 and figure 27 convert pulse width t 1 10 ns time between conversions t 2 10 s cnvst low to busy high delay t 3 35 ns busy high all modes except master serial read after convert t 4 1.25 s aperture delay t 5 2 ns end of conversion to busy low delay t 6 10 ns conversion time t 7 1.25 s acquisition time t 8 8.75 s reset pulse width t 9 10 ns refer to figure 28, figure 29, and (parallel interface modes) cnvst low to data valid delay t 10 1.25 s data valid to busy low delay t 11 12 ns bus access request to data valid t 12 45 ns bus relinquish time t 13 5 15 ns refer to figure 32 and figure 33 (master serial interface modes) 1 cs low to sync valid delay t 14 10 ns cs low to internal sclk valid delay 1 t 15 10 ns cs low to sdout delay t 16 10 ns cnvst low to sync delay t 17 525 ns sync asserted to sclk first edge delay t 18 3 ns internal sclk period 2 t 19 25 40 ns internal sclk high 2 t 20 12 ns internal sclk low 2 t 21 7 ns sdout valid setup time 2 t 22 4 ns sdout valid hold time 2 t 23 2 ns sclk last edge to sync delay 2 t 24 3 ns cs high to sync hi-z t 25 10 ns cs high to internal sclk hi-z t 26 10 ns cs high to sdout hi-z t 27 10 ns busy high in master serial read after convert 2 t 28 see table 4 cnvst low to sync asserted delay t 29 1.25 s sync deasserted to busy low delay t 30 25 ns refer to and (slave serial interface modes) 1 external sclk setup time t 31 5 ns external sclk active edge to sdout delay t 32 3 18 ns sdin setup time t 33 5 ns sdin hold time t 34 5 ns external sclk period t 35 25 ns external sclk high t 36 10 ns external sclk low t 37 10 ns figure 30 figure 34 figure 35 1 in serial interface modes, the sync, sclk, an d sdout timings are defined with a maximum load c l of 10 pf; otherwise, the load is 60 pf maximum. 2 in serial master read during convert mode. see ta ble 4 for serial master re ad after convert mode. rev. 0 | page 5 of 28
ad7651 table 4. serial clock timings in master read after convert divsclk[1] 0 0 1 1 divsclk[0] symbol 0 1 0 1 unit sync to sclk first edge delay minimum t 18 3 17 17 17 ns internal sclk period minimum t 19 25 50 100 200 ns internal sclk period maximum t 19 40 70 140 280 ns internal sclk high minimum t 20 12 22 50 100 ns internal sclk low minimum t 21 7 21 49 99 ns sdout valid setup time minimum t 22 4 18 18 18 ns sdout valid hold time minimum t 23 2 4 30 80 ns sclk last edge to sync delay minimum t 24 3 55 130 290 ns busy high width maximum t 24 2 2.5 3.5 5.75 s rev. 0 | page 6 of 28
ad7651 absolute maximum ratings table 5. ad7651 stress ratings 1 in 2 , temp 2 ,ref, refbufin, ingnd, refgnd to agnd avdd + 0.3 v to agnd C 0.3 v ground voltage differences agnd, dgnd, ognd 0.3 v supply voltages avdd, dvdd, ovdd C0.3 v to +7 v avdd to dvdd, avdd to ovdd 7 v dvdd to ovdd C0.3 v to +7 v digital inputs C0.3 v to dvdd + 0.3 v pdref, pdbuf 3 20 ma internal power dissipation 4 700 mw internal power dissipation 5 2.5 w junction temperature 150c storage temperature range C65c to +150c lead temperature range (soldering 10 sec) 300c 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the de vice. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this spec ification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 see section. 3 see section. 4 specification is for the device in free air: 48-lead lqfp; ja = 91c/w, jc = 30c/w 5 specification is for the device in free air: 48-lead lfcsp; ja = 26c/w. analog input voltage reference input i oh 500 a 1.6ma i ol to output pin 1.4v c l 60pf* * in serial interface modes,the sync, sclk, and sdout timings are defined with a maximum load c l of 10pf; otherwise,the load is 60pf maximum. 02964-0-006 figure 2. load circuit for digital interface timing, sdout, sync, sclk outputs c l = 10 pf 0.8v 2v 2v 0.8v 0.8v 2v t delay t delay 02965-0-007 figure 3. voltage reference levels for timing esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. rev. 0 | page 7 of 28
ad7651 pin configuration and function descriptions 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) agnd cnvst pd reset cs rd dgnd agnd avdd nc byteswap ob/2c nc nc nc = no connect ser/par d0 d1 busy d15 d14 d13 ad7651 d3/divsclk1 d12 d4/ext/int d5/invsync d6/invsclk d7/rdc/sdin ognd ovdd dvdd dgnd d8/sdout d9/sclk d10/sync d11/rderror pdbuf pdref refbufin temp avdd in agnd agnd nc ingnd refgnd ref 02965-0-002 d2/divsclk0 figure 4. 48-lead lqfp (st- 48) and 48-lead lfcsp (cp-48) table 6. pin function descriptions pin no. mnemonic type 1 description 1, 36, 41, 42 agnd p analog power ground pin. 2, 44 avdd p input analog power pin. nominally 5 v. 3, 6, 7, 40 nc no connect. 4 byteswap di parallel mode selection (8 -/16-bit). when low, the lsb is output on d[7:0] and the msb is output on d[15:8]. when high, the lsb is output on d[15:8] and the msb is output on d[7:0]. 5 ob/2c di straight binary/binary twos complement. when ob/2c is high, the digital output is straight binary; when low, the msb is inverted, resulting in a twos complement output fr om its internal shift register. 8 ser/par di serial/parallel selection input. when low, th e parallel port is selected; when high, the serial interface mode is selected and some bits of the data bus are used as a serial port. 9, 10 d[0:1] do bit 0 and bit 1 of the parallel po rt data output bus. when ser/par is high, these outputs are in high impedance. 11, 12 d[2:3]or divsclk[0:1] di/o when ser/par is low, these outputs are us ed as bit 2 and bit 3 of the parallel port data output bus. when ser/par is high, ext/int is low, and rdc/sdin is low (s erial master read after convert), these inputs, part of the serial port, are used to slo w down, if desired, the internal serial clock that clocks the data output. in other seri al modes, these pins are not used. 13 d4 or ext/int di/o when ser/par is low, this output is used as bit 4 of the parallel port data output bus. when ser/par is high, this input, part of the serial port, is used as a digital select input for choosing the internal data clock or an ex ternal data clock. with ext/int tied low, the internal clock is selected on the sclk output. with ext/int set to a logic high, output data is synchronized to an external clock signal connected to the sclk input. 14 d5 or invsync di/o when ser/par is low, this output is used as bit 5 of the parallel port data output bus. when ser/par is high, this input, part of the serial port, is used to select the active state of the sync signal. it is active in both master and slave mode s. when low, sync is active high. when high, sync is active low. 15 d6 or invsclk di/o when ser/par is low, this output is used as bit 6 of the parallel port data output bus. when ser/par is high, this input, part of the serial port, is used to invert the sc lk signal. it is active in both master and slave modes. rev. 0 | page 8 of 28
ad7651 pin no. mnemonic type 1 description 16 d7 or rdc/sdin di/o when ser/par is low, this output is used as bit 7 of the parallel port data output bus. when ser/par is high, this input, part of the serial port, is used as either an ex ternal data input or a read mode selection input depending on the state of ext/int . when ext/int is high, rdc/sdin could be used as a data input to dais y-chain the conversion results from two or more adcs onto a single sdout line. the digital data level on sdin is output on data with a delay of 16 sclk periods after the initiation of the read sequence. when ext/int is low, rdc/sdin is used to select the read mode. when rdc/sd in is high, the data is output on sdout during conversion. when rdc/ sdin is low, the data can be output on sdout only when the conversion is complete. 17 ognd p input/output interface digital power ground. 18 ovdd p input/output interface digital power. nominally at the same supply as the host interface (5 v or 3 v). 19 dvdd p digital power. nominally at 5 v. 20 dgnd p digital power ground. 21 d8 or sdout do when ser/par is low, this output is used as bit 8 of the parallel port data output bus. when ser/par is high, this output, part of the serial port, is used as a serial data output synchronized to sclk. conversion results are stor ed in an on-chip register. the ad7651 provides the conversion result, msb first, from its internal shif t register. the data format is determined by the logic level of ob/2c . in serial mode when ext/int is low, sdout is valid on both edges of sclk. in serial mode when ext/int is high, if invsclk is low, sdout is updated on the sclk rising edge and valid on the next falling edge; if invsclk is high , sdout is updated on th e sclk falling edge and valid on the next rising edge. 22 d9 or sclk di/o when ser/par is low, this output is used as bit 9 of the parallel port data or sclk output bus. when ser/par is high, this pin, part of the serial port, is used as a serial data clock input or output, depending upon the logic state of the ext/int pin. the active edge where the data sdout is updated depends upon the logic state of the invsclk pin. 23 d10 or sync do when ser/par is low, this output is used as bit 10 of the parallel port data output bus. when ser/par is high, this output, part of the serial port, is used as a digital output frame synchronization for use with th e internal data clock (ext/int = logic low). when a read sequence is initiated and invsync is low, sy nc is driven high and remains high while the sdout output is valid. when a read sequence is initiated and invsync is high, sync is driven low and remains low while the sdout output is valid. 24 d11 or rderror do when ser/par is low, this output is us ed as bit 11 of the parallel port data output bus. when ser/par and ext/int are high, this output, part of the serial port, is used as an incomplete read error flag. in slave mode, when a data read is started an d not complete when the following conversion is complete, the current data is lo st and rderror is pulsed high. 25C28 d[12:15] do bit 12 to bit 15 of the parallel port data o utput bus. these pins are alwa ys outputs regardless of the state of ser/par . 29 busy do busy output. transitions high when a conversi on is started and remains high until the conversion is complete and the data is latched into the on-chip shift register. the falling edge of busy could be used as a data ready clock signal. 30 dgnd p must be tied to digital ground. 31 rd di read data. when cs and rd are both low, the interface parallel or serial output bus is enabled. 32 cs di chip select. when cs and rd are both low, the interface parallel or serial output bus is enabled. cs is also used to gate the external clock. 33 reset di reset input. when set to a logic high, this pin resets the ad7651 and the current conversion, if any, is aborted. if not used, this pin could be tied to dgnd. 34 pd di power-down input. when set to a logic high , power consumption is reduced and conversions are inhibited after the current one is completed. 35 cnvst di start conversion. if cnvst is high when the acquisition phase (t 8 ) is complete, the next falling edge on cnvst puts the internal sample/hold into the hold state and initiates a conversion. the mode is most appropriate if low sampling jitter is desired. if cnvst is low when the acquisition phase (t 8 ) is complete, the internal sample/hol d is put into the hold state and a conversion is immediately started. 37 ref ai/o reference input voltage. on-chip reference output voltage. 38 refgnd ai reference input analog ground. 39 ingnd ai analog input ground. rev. 0 | page 9 of 28
ad7651 pin no. mnemonic type 1 description 43 in ai primary analog input with a range of 0 v to 2.5 v. 45 temp ao temperature sensor voltage output. 46 refbufin ai/o reference input voltage. the re ference output and the reference buffer input. 47 pdref di this pin allows the choice of internal or external voltage references. when low, the on-chip reference is turned on. when high, the internal re ference is switched off and an external reference must be used. 48 pdbuf di this pin allows the choice of buffering an in ternal or external referenc e with the internal buffer. when low, the buffer is selected. wh en high, the buffer is switched off. 1 ai = analog input; ai/o = bidirectional analog; ao = analog output; di = digital input; di/o = bidirectional digital; do = digi tal output; p = power. rev. 0 | page 10 of 28
ad7651 definitions of specifications integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. full-scale error the last transition (from 01110 to 01111 in twos complement coding) should occur for an analog voltage 1? lsb below the nominal full scale (2.49994278 v for the 0 v to 2.5 v range). the full-scale error is the deviation of the actual level of the last transition from the ideal level. unipolar zero error the first transition should occur at a level ? lsb above analog ground (19.073 v for the 0 v to 2.5 v range). unipolar zero error is the deviation of the actual transition from that point. spurious-free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to s/( n + d ) by the following formula: enob = ( s/[ n + d ] db C 1.76)/6.02 and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal, and is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal-to-(noise + distortion) ratio (s/[n+d]) s/(n+d) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/(n+d) is expressed in decibels. aperture delay aperture delay is a measure of the acquisition performance and is measured from the falling edge of the cnvst input to when the input signal is held for a conversion. transient response transient response is the time required for the ad7651 to achieve its rated accuracy after a full-scale step function is applied to its input. overvoltage recovery overvoltage recovery is the time required for the adc to recover to full accuracy after an analog input signal 150% of the full-scale value is reduced to 50% of the full-scale value. reference voltage temperature coefficient reference voltage temperature coefficient is the change of internal reference voltage output voltage v over the operating temperature range and normalized by the output voltage at 25c, expressed in ppm/c. the equation follows: 6 12 12 10 )C()c25( )(C)( )/( = tt v tvtv cppmtcv where: v (25 c ) = v at +25c v ( t 2 ) = v at temperature 2 (+85c) v ( t 1 ) = v at temperature 1 (C40c) rev. 0 | page 11 of 28
ad7651 rev. 0 | page 12 of 28 typical performance characteristics code inl (lsb) 0 ?4 ?3 ?1 ?2 0 3 2 1 4 16384 32768 65536 49152 02964-0-026 figure 5. integral nonlinearity vs. code code in hex counts 7ffb 0 20000 60000 40000 80000 140000 120000 8000 8001 8003 8002 02964-0-027 8004 7ffc 7ffd 7ffe 7fff 100000 10822 00 0 0 137 479 20890 114686 114156 figure 6. histogram of 261,120 conversions of a dc input at the code transition frequency (khz) amplitude (db of full scale) 0 ?180 ?160 ?120 ?140 ?100 ?60 ?80 0 20 30 50 40 02964-0-029 10 ?40 ?20 f s = 100ksps f in = 45.7khz snr = 86.7db thd = 102.5db sfdr = 103.6db s/[n+d] = 86.6db figure 7. fft plot code dnl (lsb) 0 ?1.0 ?0.5 0 1.5 1.0 0.5 2.0 16384 32768 65536 49152 02964-0-023 figure 8. differential nonlinearity vs. code code in hex counts 0 20000 80000 40000 100000 180000 120000 8000 8001 8003 8002 02964-0-028 8004 7ffc 7ffd 7ffe 7fff 019 2896 1903 50 60000 155528 49184 51585 140000 160000 figure 9. histogram of 261,120 conversions of a dc input at the code center frequency (khz) snr, s/[n+d] (db) 1 80 85 87 86 88 90 100 02964-0-030 1000 10 89 enob (bits) 15.5 13.0 13.5 14.0 14.5 15.0 enob snr s/[n+d] 81 83 82 84 figure 10. snr, s/(n+d), and enob vs. frequency
ad7651 rev. 0 | page 13 of 28 frequency (khz) thd, harmonics (db) 1 ?120 ?100 ?90 ?70 100 02964-0-031 1000 10 ?80 sfdr (db) 120 100 20 40 60 80 second harmonic sfdr third harmonic thd 110 90 30 50 70 ?105 ?95 ?75 ?85 ?115 ?110 figure 11. thd, harmonics, and sfdr vs. frequency input level (db) snr, s/[n+d] referred to full scale (db) ?60 85 90 02964-0-032 0 ?50 ?40 ?30 ?20 ?10 86 87 88 89 snr s/[n+d] figure 12. snr and s/(n+d) vs. input level (referred to full scale) 15.5 13.5 14.0 14.5 15.0 temperature (db) snr, s/[n+d] (db) ?55 85 89 02964-0-033 125 ?35 ?15 5 25 45 86 87 88 snr 65 10585 s/[n+d] enob (bits) figure 13. snr, s/(n+d), and enob vs. temperature temperature (c) thd, harmonics (db) ?55 ?120 ?100 02964-0-034 125 ?35 ?15 25 45 65 ?115 ?105 second harmonic 58 5 105 third harmonic thd ?110 figure 14. thd and harmonics vs. temperature sample rate (sps) 02964-0-035 100 10000 100000 1 100 1000 10 1000 10000 0.001 0.1 0.01 operating current ( a) dvdd pdref = pdbuf = high 10 avdd ovdd figure 15. operating current vs. sample rate temperature (c) zero error, full scale (lsb) ?55 6 02964-0-036 ?35 5 25 45 65 ?15 85 125 4 5 2 3 0 1 ?4 ?3 ?6 ?5 105 full scale zero error ?2 ?1 figure 16. zero error, full scale with reference vs. temperature
ad7651 rev. 0 | page 14 of 28 temperature (c) vref (v) ?40 2.5042 02964-0-037 0204060 ?20 80 120 2.5028 100 2.5030 2.5032 2.5034 2.5036 2.5038 2.5040 figure 17. typical reference output voltage vs. temperature reference drift (ppm/c) number of units ?30 0 10 25 02965-0-040 ?26 ?22 ?18 ?14 15 ?10 ?6 ?2 2 30 26221814106 5 20 figure 18. reference voltage temperature coefficient distribution (100 units) c l (pf) t 12 delay (ns) 0 0 50 02964-0-039 200 50 100 150 10 30 40 20 ovdd = 5v @ 25c ovdd = 5v @ 85c ovdd = 2.7v @ 25c ovdd = 2.7v @ 85c figure 19. typical delay vs. load capacitance c l
ad7651 circuit information sw a comp sw b in ref refgnd lsb msb 32,768c ingnd 16,384c 4c 2c c c 65,536c control logic switches control busy output code 02964-0-005 cnvst figure 20. adc simplified schematic igure 20 the ad7651 is a very fast, low power, single supply, precise 16-bit analog-to-digital converter (adc). during the acquisition phase, the common terminal of the array tied to the comparator's positive input is connected to agnd via sw a . all independent switches are connected to the analog input in. thus, the capacitor array is used as a sampling capacitor and acquires the analog signal on in. similarly, the dummy capacitor acquires the analog signal on ingnd. the ad7651 provides the user with an on-chip track/hold, successive approximation adc that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. when cnvst goes low, a conversion phase is initiated. when the conversion phase begins, sw a and sw b are opened. the capacitor array and dummy capacitor are then disconnected from the inputs and connected to refgnd. therefore, the differential voltage between in and ingnd captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between refgnd and ref, the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4, v ref /65536). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. the ad7651 can be operated from a single 5 v supply and can be interfaced to either 5 v or 3 v digital logic. it is housed in either a 48-lead lqfp or a 48-lead lfcsp that saves space and allows flexible configurations as either a serial or parallel inter- face. the ad7651 is pin-to-pin compatible with pulsar adcs. converter operation the ad7651 is a successive-approximation adc based on a charge redistribution dac. f shows a simplified sche- matic of the adc. the capacitive dac consists of an array of 16 binary weighted capacitors and an additional lsb capacitor. the comparators negative input is connected to a dummy capacitor of the same value as the capacitive dac array. after this process is completed, the control logic generates the adc output code and brings the busy output low. rev. 0 | page 15 of 28
ad7651 transfer functions using the ob/ 2c digital input, the ad7651 offers two output codings: straight binary and twos complement. the lsb size is v ref /65536, which is about 38.15 v. the ad7651s ideal transfer characteristic is shown in and . figure 21 figure 21. adc ideal transfer function table 7 table 7. output codes and ideal input voltages 000...000 000...001 000...010 111...101 111...110 111...111 adc code (straight binary) analog input v ref ? 1.5 lsb v ref ? 1 lsb 1lsb 0v 0.5 lsb 1 lsb = v ref /65536 02964-0-003 digital output code (hex) description analog input straight binary twos complement fsr C1 lsb 2.499962 v ffff 1 7fff1 fsr C 2 lsb 2.499923 v fffe 7ffe midscale + 1 lsb 1.250038 v 8001 0001 midscale 1.25 v 8000 0000 midscale C 1 lsb 1.249962 v 7fff ffff Cfsr + 1 lsb 38 v 0001 8001 Cfsr 0 v 0000 2 8000 2 1 this is also the code for overrange analog input (v in C v ingnd above v ref C v refgnd ). 2 this is also the code for underrange analog input (v in below v ingnd ). notes 1 the configuration shown is using the internal reference and internal buffer. 2 the ad8021 is recommended. see driver amplifier choice section. 3 optional low jitter. 4 a 10 f ceramic capacitor (x5r, 1206 size) is recommended (e.g., panasonic ecj3yb0j106m). see voltage reference input section. ad7651 d 3 clock c/ p/dsp serial port digital supply (3.3v or 5v) dvdd 100nf + 10 f 100nf + 10 f 20 ? 100nf + 10 f analog supply (5v) c c a nalog inpu t (0v to 2.5v) pd reset ser/par ob/2c busy sdout sclk ingnd in refgnd ref agnd avdd dgnd dvdd ovdd ognd 02964-0-004 u1 2 pdref pdbuf rd cs cnvst refbufin 1 100nf byteswap c r 4 figure 22. typical connection diagram rev. 0 | page 16 of 28
ad7651 driver amplifier choice typical connection diagram although the ad7651 is easy to drive, the driver amplifier needs to meet the following requirements: figure 22 shows a typical connection diagram for the ad7651. analog input ? the driver amplifier and the ad7651 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). in the amplifiers data sheet, settling at 0.1% to 0.01% is more commonly speci- fied. this could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection. the tiny op amp op184, which combines ultra low noise and high gain-bandwidth, meets this settling time requirement. figure 23 figure 23. equivalent analog input circuit shows an equivalent circuit of the input structure of the ad7651. the two diodes, d1 and d2, provide esd protection for the analog inputs in and ingnd. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 v. this will cause these diodes to become forward-biased and start conducting current. these diodes can handle a forward-biased current of 100 ma maximum. for instance, these conditions could eventually occur when the input buffers (u1) supplies are different from avdd. in such a case, an input buffer with a short-circuit current limitation can be used to protect the part. ? the noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the snr and transition noise performance of the ad7651. the noise coming from the driver is filtered by the ad7651 analog input circuit 1-pole low-pass filter made by r1 and c2 or by the external filter, if one is used. c2 r1 d1 d2 c1 in o r ingnd agnd av d d 02965-0-008 ? the driver needs to have a thd performance suitable to that of the ad7651. the op184 , op162 or ad8519 meet these requirements and are usually appropriate for almost all applications. as an alternative, in very high speed and noise-sensitive applications, the ad8021 with an external 10 pf compensation capacitor can be used. this capacitor should have good linearity as an npo ceramic or mica type. moreover, the use of a noninverting +1 gain arrangement is recommended and helps to obtain the best signal-to-noise ratio. this analog input structure allows the sampling of the differential signal between in and ingnd. unlike other converters, ingnd is sampled at the same time as in. by using this differential input, small signals common to both inputs are rejected. for instance, by using ingnd to sense a remote signal ground, ground potential differences between the sensor and the local adc ground are eliminated. the ad8022 could also be used if a dual version is needed and gain of 1 is present. the ad829 is an alternative in applications where high frequency (above 100 khz) performance is not required. in gain of 1 applications, it requires an 82 pf compensation capacitor. the ad8610 is an option when low bias current is needed in low frequency applications. during the acquisition phase, the impedance of the analog input in can be modeled as a parallel combination of capacitor c1 and the network formed by the series connection of r1 and c2. c1 is primarily the pin capacitance. r1 is typically 3250 ? and is a lumped component made up of some serial resistors and the on resistance of the switches. c2 is typically 60 pf and is mainly the adc sampling capacitor. during the conversion phase, where the switches are opened, the input impedance is limited to c1. r1 and c2 make a 1-pole low-pass filter that reduces undesirable aliasing effect and limits the noise. when the source impedance of the driving circuit is low, the ad7651 can be driven directly. large source impedances will significantly affect the ac performance, especially total harmonic distortion. rev. 0 | page 17 of 28
ad7651 voltage reference input the ad7651 allows the choice of either a very low temperature drift internal voltage reference or an external 2.5 v reference. for applications that use multiple ad7651s, it is more effective to use the internal buffer to buffer the reference voltage. unlike many adcs with internal references, the internal reference of the ad7651 provides excellent performance and can be used in almost all applications. care should be taken with the voltage references temperature coefficient, which directly affects the full-scale accuracy if this parameter matters. for instance, a 15 ppm/c temperature coefficient of the reference changes full scale by 1 lsb/c. to use the internal reference along with the internal buffer, pdref and pdbuf should both be low. this will produce a 1.207 v voltage on refbufin which, amplified by the buffer, will result in a 2.5 v reference on the ref pin. note that v ref can be increased to avdd C 1.85 v. since the input range is defined in terms of v ref , this would essentially increase the range to 0 v to 3 v with an avdd above 4.85 v. the ad780 can be selected with a 3 v reference voltage. the output impedance of refbufin is 11 k ? (minimum) when the internal reference is enabled. it is useful to decouple refbufin with a 100 nf ceramic capacitor. thus, the 100 nf capacitor provides an rc filter for noise reduction. the temp pin, which measures the temperature of the ad7651, can be used as shown in . the output of temp pin is applied to one of the inputs of the analog switch (e.g., adg779 ), and the adc itself is used to measure its own temperature. this configuration is very useful for improving the calibration accuracy over the temperature range. figure 24 figure 24. temperature sensor connection diagram to use an external reference along with the internal buffer, pdref should be high and pdbuf should be low. this powers down the internal reference and allows the 2.5 v reference to be applied to refbufin. adg779 ad8021 c c 02964-0-024 analog input (unipolar) ad7651 in temperature sensor temp to use an external reference directly on ref pin, pdref and pdbuf should both be high. pdref and pdbuf respectively power down the internal reference and the internal reference buffer. note that the pdref and pdbuf input current should never exceed 20 ma. this could eventually occur when input voltage is above avdd (for instance at power up). in this case, a 100 ? series resistor is recommended. power supply the ad7651 uses three power supply pins: an analog 5 v supply avdd, a digital 5 v core supply dvdd, and a digital input/ output interface supply ovdd. ovdd allows direct interface with any logic between 2.7 v and dvdd + 0.3 v. to reduce the supplies needed, the digital core (dvdd) can be supplied through a simple rc filter from the analog supply, as shown in . the ad7651 is independent of power supply sequencing once ovdd does not exceed dvdd by more than 0.3 v, and is thus free of supply voltage induced latch-up. the internal reference is temperature compensated to 2.5 v 20 mv. the reference is trimmed to provide a typical drift of 7 . this typical drift characteristic is shown in . for improved drift performance, an external reference such as the ad780 can be used. ppm/c figure 17 figure 22 the ad7651 voltage reference input ref has a dynamic input impedance; it should therefore be driven by a low impedance source with efficient decoupling between the ref and refgnd inputs. this decoupling depends on the choice of the voltage reference but usually consists of a low esr tantalum capacitor connected to ref and refgnd with minimum parasitic inductance. a 10 f (x5r, 1206 size) ceramic chip capacitor (or 47 f tantalum capacitor) is appropriate when using either the internal reference or one of these recommended reference voltages: ? the low noise, low temperature drift adr421 and ad780 ? the low power adr291 ? the low cost ad1582 rev. 0 | page 18 of 28
ad7651 power dissipation versus throughput the cnvst trace should be shielded with ground and a low value serial resistor (i.e., 50 ?) termination should be added close to the output of the component that drives this line. operating currents are very low during the acquisition phase, allowing significant power savings when the conversion rate is reduced (see ). the ad7651 automatically reduces its power consumption at the end of each conversion phase. this makes the part ideal for very low power battery applications. the digital interface and the reference remain active even during the acquisition phase. to reduce operating digital supply currents even further, digital inputs need to be driven close to the power supply rails (i.e., dvdd or dgnd), and ovdd should not exceed dvdd by more than 0.3 v. figure 25 figure 25. power dissipation vs. sampling rate for applications where snr is critical, the cnvst signal should have very low jitter. this may be achieved by using a dedicated oscillator for cnvst generation, or to clock cnvst with a high frequency, low jitter clock, as shown in . figure 22 busy mode t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 acquire convert acquire convert 02964-0-011 cnvst 100000 power dissipation ( w) sampling rate (sps) 100k 1k 10 100 10k 10000 1000 100 10 02964-0-038 pdref = pdbuf = pdhigh conversion control figure 26 figure 26. basic conversion timing t 9 t 8 reset data busy 02964-0-011 cnvst shows the detailed timing diagrams of the conversion process. the ad7651 is controlled by the cnvst signal, which initiates conversion. once initiated, it cannot be restarted or aborted, even by the power-down input pd, until the conversion is complete. cnvst operates independently of cs and rd . figure 27. reset timing conversions can be automatically initiated with the ad7651. if cnvst is held low when busy is low, the ad7651 controls the acquisition phase and automatically initiates a new conversion. by keeping cnvst low, the ad7651 keeps the conversion process running by itself. it should be noted that the analog input must be settled when busy goes low. also, at power-up, cnvst should be brought low once to initiate the conversion process. in this mode, the ad7651 can run slightly faster than the guaranteed 100 ksps. t 1 t 3 t 4 t 11 busy data bus cs = rd = 0 t 10 previous conversion data new data 02964-0-012 cnvst although cnvst is a digital signal, it should be designed with special care with fast, clean edges, and levels with minimum overshoot and undershoot or ringing. figure 28. master parallel data timing for reading (continuous read) rev. 0 | page 19 of 28
ad7651 current conversion busy data bus t 12 t 13 02964-0-013 rd cs digital interface the ad7651 has a versatile digital interface; it can be interfaced with the host system by using either a serial or a parallel interface. the serial interface is multiplexed on the parallel data bus. the ad7651 digital interface also accommodates both 3 v and 5 v logic by simply connecting the ovdd supply pin of the ad7651 to the host system interface digital supply. finally, by using the ob/ 2c input pin, both twos complement or straight binary coding can be used. the two signals, cs and rd , control the interface. cs and rd have a similar effect because they are ord together internally. when at least one of these signals is high, the interface outputs are in high impedance. usually cs allows the selection of each ad7651 in multicircuit applications and is held low in a single ad7651 design. rd is generally used to enable the conversion result on the data bus. parallel interface the ad7651 is configured to use the parallel interface when ser/ par is held low. the data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion, as shown in f and , respectively. when the data is read during the conversion, however, it is recommended that it is read only during the first half of the conversion phase. this avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. igure 29 figure 29. slave parallel data timing for reading (read after convert) figure 30 figure 30. slave parallel data timing for reading (read during convert) previous conversion t 1 t 3 t 12 t 13 t 4 busy data bus 02964-0-014 cnvst, rd cs = 0 the byteswap pin allows a glueless interface to an 8-bit bus. as shown in , the lsb byte is output on d[7:0] and the msb is output on d[15:8] when byteswap is low. when byteswap is high, the lsb and msb bytes are swapped and the lsb is output on d[15:8] and the msb is output on d[7:0]. by connecting byteswap to an address line, the 16-bit data can be read in two bytes on either d[15:8] or d[7:0]. figure 31 figure 31. 8-bit parallel interface cs rd byteswap pins d[15:8] pins d[7:0] hi-z hi-z high byte low byte low byte high byte hi-z hi-z t 12 t 12 t 13 02964-0-025 serial interface the ad7651 is configured to use the serial interface when ser/ par is held high. the ad7651 outputs 16 bits of data, msb first, on the sdout pin. this data is synchronized with the 16 clock pulses provided on the sclk pin. the output data is valid on both the rising and falling edges of the data clock. rev. 0 | page 20 of 28
ad7651 master serial interface usually, because the ad7651 has a longer acquisition phase than the conversion phase, the data is read immediately after conversion. this makes the master read after conversion the most recom- mended serial mode when it can be used. in this mode, it should be noted that unlike in other modes, the busy signal returns low after the 16 data bits are pulsed out and not at the end of the conversion phase, which results in a longer busy width. internal clock the ad7651 is configured to generate and provide the serial data clock sclk when the ext/ int pin is held low. the ad7651 also generates a sync signal to indicate to the host when the serial data is valid. the serial clock sclk and the sync signal can be inverted if desired. depending on the rdc/sdin input, the data can be read after each conversion or during the following conversion. figure 32 and figure 33 show detailed timing diagrams of these two modes. in the read during conversion mode, the serial clock and data toggle at appropriate instants, which minimize potential feed- through between digital activity and critical conversion decisions t 3 busy sync sclk sdout t 28 t 29 t 14 t 18 t 19 t 20 t 21 t 24 t 26 t 27 t 23 t 22 t 16 t 15 12 3 141516 d15 d14 d2 d1 d0 x rdc/sdin = 0 invsclk = invsync = 0 t 25 t 30 02964-0-015 cnvst cs, rd ext/int = 0 figure 32. master serial data timi ng for reading (read after convert) ext/int = 0 rdc/sdin = 1 invsclk = invsync = 0 t 3 t 1 t 17 t 14 t 19 t 20 t 21 t 24 t 26 t 25 t 27 t 23 t 22 t 16 t 15 d15 d14 d2 d1 d0 x 12 3 141516 t 18 busy sync sclk sdout 02964-0-016 cnvst cs, rd figure 33. master serial data timing for read ing (read previous conversion during convert) rev. 0 | page 21 of 28
ad7651 slave serial interface external clock the ad7651 is configured to accept an externally supplied serial data clock on the sclk pin when the ext/ int pin is held high. in this mode, several methods can be used to read the data. the external serial clock is gated by cs . when cs and rd are both low, the data can be read after each conversion or during the following conversion. the external clock can be either a continuous or a discontinuous clock. a discontinuous clock can be either normally high or normally low when inactive. f and f show the detailed timing diagrams of these methods. usually, because the ad7651 has a longer acquisition phase than conversion phase, the data are read immediately after conversion. igure 34 figure 34. slave serial data timing for reading (read after convert) igure 35 figure 35. slave serial data timing for readin g (read previous conversion during convert) while the ad7651 is performing a bit decision, it is important that voltage transients be avoided on digital input/output pins or degradation of the conversion result could occur. this is particularly important during the second half of the conversion phase because the ad7651 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. for this reason, it is recommended that when an external clock is being provided, it is a discontinuous clock that is toggling only when busy is low, or, more importantly, that it does not transition during the latter half of busy high. sclk sdout d15 d14 d1 d0 d13 x15 x14 x13 x1 x0 y15 y14 busy sdin invsclk = 0 t 35 t 36 t 37 t 31 t 32 t 16 t 33 x15 x14 x 1 2 3 14151617 18 t 34 02964-0-017 ext/int = 1 rd rd = 0 s dout sclk d1 d0 x d15 d14 d13 123 141516 t 3 t 35 t 36 t 37 t 31 t 32 t 16 busy ext/int = 1 invsclk = 0 02965-0-018 cnvst cs rd = 0 rev. 0 | page 22 of 28
ad7651 external discontinuous clock data read after conversion external clock data read during conversion figure 35 shows the detailed timing diagrams of this method. during a conversion, while both cs and rd are low, the result of the previous conversion can be read. the data is shifted out msb first with 16 clock pulses, and is valid on both the rising and falling edges of the clock. the 16 bits must be read before the current conversion is complete; otherwise, rderror is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. there is no daisy-chain feature in this mode and the rdc/sdin input should always be tied either high or low. though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. shows the detailed timing diagrams of this method. after a conversion is complete, indicated by busy returning low, the conversions result can be read while both cs and rd are low. data is shifted out msb first with 16 clock pulses and is valid on the rising and falling edges of the clock. figure 34 among the advantages of this method is the fact that conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. another advantage is the ability to read the data at any speed up to 40 mhz, which accommodates both the slow digital host interface and the fastest serial reading. to reduce performance degradation due to digital activity, a fast discontinuous clock of at least 18 mhz is recommended to ensure that all the bits are read during the first half of the conversion phase. it is also possible to begin to read data after conversion and continue to read the last bits after a new conversion has been initiated. this allows the use of a slower clock speed like 14 mhz. finally, in this mode only, the ad7651 provides a daisy-chain feature using the rdc/sdin pin for cascading multiple con- verters together. this feature is useful for reducing component count and wiring connections when desired, as, for instance, in isolated multiconverter applications. an example of the concatenation of two devices is shown in . simultaneous sampling is possible by using a common cnvst signal. it should be noted that the rdc/sdin input is latched on the opposite edge of sclk of the one used to shift out the data on sdout. therefore, the msb of the upstream converter just follows the lsb of the downstream converter on the next sclk cycle. figure 36 figure 36. two ad7651s in a daisy-chain configuration sclk sdout rdc/sdin busy busy data out ad7651 #1 (downstream) busy out sclk ad7651 #2 (upstream) rdc/sdin sdout sclk in cnvst in 02964-0-019 cnvst cs cnvst cs cs in rev. 0 | page 23 of 28
ad7651 microprocessor interfacing the ad7651 is ideally suited for traditional dc measurement applications supporting a microprocessor, and for ac signal processing applications interfacing to a digital signal processor. the ad7651 is designed to interface either with a parallel 8-bit or 16-bit wide interface, or with a general-purpose serial port or i/o ports on a microcontroller. a variety of external buffers can be used with the ad7651 to prevent digital noise from coupling into the adc. the following section discusses the use of an ad7651 with an adsp-219x spi equipped dsp. spi interface (adsp-219x) figure 37 figure 37. interfacing the ad7651 to an spi interfac shows an interface diagram between the ad7651 and the spi equipped adsp-219x. to accommodate the slower speed of the dsp, the ad7651 acts as a slave device and data must be read after conversion. this mode also allows the daisy- chain feature. the convert command can be initiated in response to an internal timer interrupt. the reading process can be initiated in response to the end-of-conversion signal (busy going low) using an interrupt line of the dsp. the serial inter- face (spi) on the adsp-219x is configured for master mode (mstr) = 1, clock polarity bit (cpol) = 0, clock phase bit (cpha) = 1, and spi interrupt enable (timod) = 00by writing to the spi control register (spicltx). to meet all timing requirements, the spi clock should be limited to 17 mbps, which allows it to read an adc result in less than 1 s. when a higher sampling rate is desired, use of one of the parallel interface modes is recommended. ad7651* adsp-219x* ser/par pfx misox sckx pfx or tfsx busy sdout sclk cnvst ext/int cs rd invsclk dvdd * additional pins omitted for clarity spixsel (pfx) 02964-0-021 rev. 0 | page 24 of 28
ad7651 application hints bipolar and wider input ranges in some applications, it is desirable to use a bipolar or wider analog input range such as 10 v, 5 v, or 0 v to 5 v. although the ad7651 has only one unipolar range, simple modifications of input driver circuitry allow bipolar and wider input ranges to be used without any performance degradation. shows a connection diagram that allows this. component values required and resulting full-scale ranges are shown in . figure 38 figure 38 figure 38. using the ad7651 in 16-bit bipolar and/or wider input ranges table 8 table 8. component values and input ranges when desired, accurate gain and offset can be calibrated by acquiring a ground and voltage reference using an analog multiplexer (u2), as shown in . u1 analog input r2 r3 r4 100nf r1 u2 c ref in ingnd ref refgnd ad7651 02964-0-022 c f input range r1 (?) r2 (k?) r3 (k?) r4 (k?) 10 v 500 4 2.5 2 5 v 500 2 2.5 1.67 0 v to C5 v 500 1 none 0 layout the ad7651 has very good immunity to noise on the power supplies. however, care should still be taken with regard to grounding layout. the printed circuit board that houses the ad7651 should be designed so the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be separated easily. digital and analog ground planes should be joined in only one place, preferably underneath the ad7651, or as close as possible to the ad7651. if the ad7651 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point that should be established as close as possible to the ad7651. running digital lines under the device should be avoided since these will couple noise onto the die. the analog ground plane should be allowed to run under the ad7651 to avoid noise coupling. fast switching signals like cnvst or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. crossover of digital and analog signals should be avoided. traces on different but close layers of the board should run at right angles to each other. this will reduce the effect of crosstalk through the board. the power supply lines to the ad7651 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. good decoupling is also important to lower the supplys impedance presented to the ad7651 and to reduce the magnitude of the supply spikes. decoupling ceramic capacitors, typically 100 nf, should be placed on each power supply pinavdd, dvdd, and ovddclose to, and ideally right up against these pins and their corresponding ground pins. additionally, low esr 10 f capacitors should be located near the adc to further reduce low frequency ripple. the dvdd supply of the ad7651 can be a separate supply or can come from the analog supply avdd or the digital interface supply ovdd. when the system digital supply is noisy or when fast switching digital signals are present, if no separate supply is available, the user should connect dvdd to avdd through an rc filter (see f ) and the system supply to ovdd and the remaining digital circuitry. when dvdd is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. igure 22 the ad7651 has five different ground pins: ingnd, refgnd, agnd, dgnd, and ognd. ingnd is used to sense the analog input signal. refgnd senses the reference voltage and, because it carries pulsed currents, should be a low impedance return to the reference. agnd is the ground to which most internal adc analog signals are referenced; it must be connected with the least resistance to the analog ground plane. dgnd must be tied to the analog or digital ground plane depending on the configuration. ognd is connected to the digital system ground. evaluating the ad7651s performance a recommended layout for the ad7651 is outlined in the eval-ad7651 evaluation board for the ad7651. the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval-control brd2 . rev. 0 | page 25 of 28
ad7651 outline dimensions top view (pins down ) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc s q seating plane 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.10 max coplanarity view a rotated 90 ccw seating plane 7 3.5 0 10 6 2 0.15 0.05 compliant to jedec standards ms-026bbc figure 39. 48-lead quad flatpack (lqfp) [st-48] dimensions shown in millimeters pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 bottom view 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane paddle connected to agnd. this connection is not required to meet the electrical performances 0.25 min 0.20 ref compliant to jedec standards mo-220-vkkd-2 figure 40. 48-lead frame chip scale package (lfcsp) [cp-48] dimensions shown in millimeters ordering guide model temperature range package description package option ad7651ast C40c to +85c quad flatpack (lqfp) st-48 ad7651astrl C40c to +85c qu ad flatpack (lqfp) st-48 ad7651acp C40c to +85c lead frame chip scale (lfcsp) cp-48 ad7651acprl C40c to +85c lead frame chip scale (lfcsp) cp-48 eval-ad7651cb 1 evaluation board eval-control brd2 2 controller board 1 this board can be used as a standalone evaluation board or in conjunction with the eval-control brd2 for evaluation/demonstrati on purposes. 2 this board allows a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. rev. 0 | page 26 of 28
ad7651 notes rev. 0 | page 27 of 28
ad7651 notes ? 2003 analog devices, inc. all ri ghts reserved. trademarks and registered trademarks are the proper ty of their respective companies. c02964C0C9/03(0) rev. 0 | page 28 of 28

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